mirror of
https://github.com/jart/cosmopolitan.git
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2fc507c98f
* modelines: tw -> sw shiftwidth, not textwidth. * space-surround modelines * fix irregular modelines * Fix modeline in titlegen.c
171 lines
5.3 KiB
ArmAsm
171 lines
5.3 KiB
ArmAsm
/*-*- mode:unix-assembly; indent-tabs-mode:t; tab-width:8; coding:utf-8 -*-│
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│ vi: set noet ft=asm ts=8 sw=8 fenc=utf-8 :vi │
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╚──────────────────────────────────────────────────────────────────────────────╝
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│ │
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│ Optimized Routines │
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│ Copyright (c) 1999-2022, Arm Limited. │
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│ │
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│ Permission is hereby granted, free of charge, to any person obtaining │
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│ a copy of this software and associated documentation files (the │
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│ "Software"), to deal in the Software without restriction, including │
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│ without limitation the rights to use, copy, modify, merge, publish, │
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│ distribute, sublicense, and/or sell copies of the Software, and to │
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│ permit persons to whom the Software is furnished to do so, subject to │
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│ the following conditions: │
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│ │
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│ The above copyright notice and this permission notice shall be │
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│ included in all copies or substantial portions of the Software. │
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│ │
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│ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, │
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│ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF │
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│ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. │
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│ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY │
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│ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, │
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│ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE │
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│ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. │
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│ │
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╚─────────────────────────────────────────────────────────────────────────────*/
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#include "libc/intrin/aarch64/asmdefs.internal.h"
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#define __strcpy_aarch64 strcpy
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.ident "\n\n\
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Optimized Routines (MIT License)\n\
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Copyright 2022 ARM Limited\n"
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.include "libc/disclaimer.inc"
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/* Assumptions:
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*
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* ARMv8-a, AArch64, Advanced SIMD.
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* MTE compatible.
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*/
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#define dstin x0
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#define srcin x1
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#define result x0
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#define src x2
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#define dst x3
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#define len x4
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#define synd x4
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#define tmp x5
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#define shift x5
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#define data1 x6
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#define dataw1 w6
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#define data2 x7
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#define dataw2 w7
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#define dataq q0
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#define vdata v0
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#define vhas_nul v1
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#define vend v2
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#define dend d2
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#define dataq2 q1
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/*
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Core algorithm:
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For each 16-byte chunk we calculate a 64-bit nibble mask value with four bits
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per byte. We take 4 bits of every comparison byte with shift right and narrow
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by 4 instruction. Since the bits in the nibble mask reflect the order in
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which things occur in the original string, counting leading zeros identifies
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exactly which byte matched. */
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ENTRY (__strcpy_aarch64)
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PTR_ARG (0)
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PTR_ARG (1)
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bic src, srcin, 15
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ld1 {vdata.16b}, [src]
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cmeq vhas_nul.16b, vdata.16b, 0
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lsl shift, srcin, 2
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shrn vend.8b, vhas_nul.8h, 4
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fmov synd, dend
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lsr synd, synd, shift
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cbnz synd, L(tail)
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ldr dataq, [src, 16]!
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cmeq vhas_nul.16b, vdata.16b, 0
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shrn vend.8b, vhas_nul.8h, 4
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fmov synd, dend
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cbz synd, L(start_loop)
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#ifndef __AARCH64EB__
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rbit synd, synd
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#endif
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sub tmp, src, srcin
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clz len, synd
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add len, tmp, len, lsr 2
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tbz len, 4, L(less16)
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sub tmp, len, 15
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ldr dataq, [srcin]
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ldr dataq2, [srcin, tmp]
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str dataq, [dstin]
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str dataq2, [dstin, tmp]
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ret
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L(tail):
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rbit synd, synd
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clz len, synd
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lsr len, len, 2
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L(less16):
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tbz len, 3, L(less8)
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sub tmp, len, 7
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ldr data1, [srcin]
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ldr data2, [srcin, tmp]
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str data1, [dstin]
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str data2, [dstin, tmp]
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ret
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.p2align 4
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L(less8):
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subs tmp, len, 3
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b.lo L(less4)
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ldr dataw1, [srcin]
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ldr dataw2, [srcin, tmp]
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str dataw1, [dstin]
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str dataw2, [dstin, tmp]
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ret
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L(less4):
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cbz len, L(zerobyte)
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ldrh dataw1, [srcin]
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strh dataw1, [dstin]
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L(zerobyte):
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strb wzr, [dstin, len]
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ret
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.p2align 4
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L(start_loop):
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sub tmp, srcin, dstin
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ldr dataq2, [srcin]
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sub dst, src, tmp
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str dataq2, [dstin]
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L(loop):
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str dataq, [dst], 32
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ldr dataq, [src, 16]
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cmeq vhas_nul.16b, vdata.16b, 0
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umaxp vend.16b, vhas_nul.16b, vhas_nul.16b
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fmov synd, dend
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cbnz synd, L(loopend)
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str dataq, [dst, -16]
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ldr dataq, [src, 32]!
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cmeq vhas_nul.16b, vdata.16b, 0
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umaxp vend.16b, vhas_nul.16b, vhas_nul.16b
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fmov synd, dend
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cbz synd, L(loop)
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add dst, dst, 16
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L(loopend):
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shrn vend.8b, vhas_nul.8h, 4 /* 128->64 */
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fmov synd, dend
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sub dst, dst, 31
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#ifndef __AARCH64EB__
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rbit synd, synd
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#endif
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clz len, synd
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lsr len, len, 2
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add dst, dst, len
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ldr dataq, [dst, tmp]
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str dataq, [dst]
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ret
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END (__strcpy_aarch64)
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