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e16a7d8f3b
`et` means `expandtab`. ```sh rg 'vi: .* :vi' -l -0 | \ xargs -0 sed -i '' 's/vi: \(.*\) et\(.*\) :vi/vi: \1 xoet\2:vi/' rg 'vi: .* :vi' -l -0 | \ xargs -0 sed -i '' 's/vi: \(.*\)noet\(.*\):vi/vi: \1et\2 :vi/' rg 'vi: .* :vi' -l -0 | \ xargs -0 sed -i '' 's/vi: \(.*\)xoet\(.*\):vi/vi: \1noet\2:vi/' ```
372 lines
14 KiB
C
372 lines
14 KiB
C
/*-*- mode:c;indent-tabs-mode:nil;c-basic-offset:2;tab-width:8;coding:utf-8 -*-│
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│ vi: set et ft=c ts=2 sts=2 sw=2 fenc=utf-8 :vi │
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╞══════════════════════════════════════════════════════════════════════════════╡
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│ Copyright 2020 Justine Alexandra Roberts Tunney │
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│ │
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│ Permission to use, copy, modify, and/or distribute this software for │
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│ any purpose with or without fee is hereby granted, provided that the │
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│ above copyright notice and this permission notice appear in all copies. │
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│ │
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│ THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL │
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│ WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED │
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│ WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE │
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│ AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL │
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│ DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR │
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│ PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER │
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│ TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR │
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│ PERFORMANCE OF THIS SOFTWARE. │
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╚─────────────────────────────────────────────────────────────────────────────*/
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#include "libc/errno.h"
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#include "libc/fmt/conv.h"
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#include "libc/intrin/safemacros.internal.h"
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#include "libc/macros.internal.h"
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#include "libc/runtime/runtime.h"
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#include "libc/stdio/stdio.h"
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#include "libc/str/str.h"
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#include "libc/sysv/consts/ex.h"
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#include "libc/sysv/consts/exit.h"
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#include "third_party/getopt/getopt.internal.h"
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#define USAGE \
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" [FLAGS] OPERAND..\n\
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Decodes geek operand notation used by ref.x86asm.net\n\
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\n\
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Flags:\n\
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-s succinct mode\n\
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-b BITS sets 16/32/64 bit mode [default 64]\n\
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-? shows this information\n\
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\n\
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Examples:\n\
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o/tool/cpu/help-operand -b64 Evqp\n\
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\n"
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int bits_;
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bool succinct_;
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void PrintUsage(int rc, FILE *f) {
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fputs("Usage: ", f);
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fputs(program_invocation_name, f);
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fputs(USAGE, f);
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exit(rc);
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}
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void GetOpts(int argc, char *argv[]) {
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int opt;
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bits_ = 64;
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while ((opt = getopt(argc, argv, "hbs")) != -1) {
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switch (opt) {
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case 's':
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succinct_ = true;
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break;
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case 'b':
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bits_ = atoi(optarg);
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break;
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case 'h':
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PrintUsage(EXIT_SUCCESS, stdout);
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default:
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PrintUsage(EX_USAGE, stderr);
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}
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}
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}
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const struct Descriptors {
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const char prefix[8];
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const char *succinct;
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const char *description;
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} kDescriptors[] = {
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{"AL", "AL", "AL register"},
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{"CS", "CS", "CS register (code segment)"},
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{"va", "?",
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"Word or doubleword, according to asz address-size attribute (only REP "
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"and LOOP families)."},
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{"dqa", "?",
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"Doubleword or quadword, according to asz address-size attribute (only "
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"REP and LOOP families)."},
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{"wa", "?",
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"Word, according to asz address-size attribute (only JCXZ instruction)."},
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{"wo", "?",
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"Word, according to current operand size (e. g., MOVSW instruction)."},
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{"ws", "?",
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"Word, according to current stack size (only PUSHF and POPF instructions "
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"in 64-bit mode)."},
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{"da", "?",
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"Doubleword, according to asz address-size attribute (only JECXZ "
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"instruction)."},
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{"do", "?",
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"Doubleword, according to current osz operand size (e. g., MOVSD "
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"instruction)."},
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{"qa", "?",
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"Quadword, according to asz address-size attribute (only JRCXZ "
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"instruction)."},
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{"qs", "64/16",
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"Quadword, according to current stack size via osz operand-size (only "
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"PUSHFQ and POPFQ instructions)."},
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{"va", "16/32",
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"Word or doubleword sign extended to the size of the stack pointer (for "
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"example, PUSH (68))."},
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{"vqp", "16/32/64",
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"Word or doubleword, depending on operand-size attribute, or "
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"quadword, promoted by REX.W in 64-bit mode."},
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{"vs", "16/32",
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"Word or doubleword sign extended to the size of the stack pointer (for "
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"example, PUSH (68))."},
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{"vds", "16/32",
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"Word or doubleword, depending on operand-size attribute, or doubleword, "
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"sign-extended to 64 bits for 64-bit operand size."},
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{"vq", "64/16",
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"Quadword (default) or word if operand-size prefix is used (for "
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"example, PUSH (50))."},
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{"EST", "STi",
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"A ModR/M byte follows the opcode and specifies the x87 FPU stack "
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"register."},
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{"ES", "STi/m",
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"A ModR/M byte follows the opcode and specifies the operand. The "
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"operand is either a x87 FPU stack register or a memory address. If "
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"it is a memory address, the address is computed from a segment "
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"register and any of the following values: a base register, an "
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"index register, a scaling factor, or a displacement."},
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{"SC", "",
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"Stack operand, used by instructions which either push an operand to the "
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"stack or pop an operand from the stack. Pop-like instructions are, for "
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"example, POP, RET, IRET, LEAVE. Push-like are, for example, PUSH, CALL, "
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"INT. No Operand type is provided along with this method because it "
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"depends on source/destination operand(s)."},
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{"BA", "m",
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"Memory addressed by DS:EAX, or by rAX in 64-bit mode (only 0F01C8 "
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"MONITOR)."},
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{"BB", "m",
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"Memory addressed by DS:eBX+AL, or by rBX+AL in 64-bit mode (only XLAT)."},
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{"BD", "m",
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"Memory addressed by DS:eDI or by RDI (only 0FF7 MASKMOVQ and 660FF7 "
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"MASKMOVDQU)"},
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{"A", "ptr",
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"Direct address. The instruction has no ModR/M byte; the address of the "
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"operand is encoded in the instruction; no base register, index register, "
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"or scaling factor can be applied (for example, far JMP (EA))."},
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{"C", "CRn",
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"The reg field of the ModR/M byte selects a control register (only MOV "
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"(0F20, 0F22))."},
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{"D", "DRn",
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"The reg field of the ModR/M byte selects a debug register (only MOV "
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"(0F21, 0F23))."},
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{"I", "imm",
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"Immediate data. The operand value is encoded in subsequent bytes of the "
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"instruction."},
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{"J", "rel",
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"The instruction contains a relative offset to be added to the "
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"instruction pointer register (for example, JMP (E9), LOOP))."},
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{"E", "r/m",
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"A ModR/M byte follows the opcode and specifies the operand. The "
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"operand is either a general-purpose register or a memory address. "
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"If it is a memory address, the address is computed from a segment "
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"register and any of the following values: a base register, an index "
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"register, a scaling factor, or a displacement."},
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{"G", "r",
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"The reg field of the ModR/M byte selects a general register (for "
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"example, AX (000))."},
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{"H", "r",
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"The r/m field of the ModR/M byte always selects a general register, "
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"regardless of the mod field (for example, MOV (0F20))."},
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{"M", "rm",
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"The ModR/M byte may refer only to memory: mod != 11bin (BOUND, LEA, "
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"CALLF, JMPF, LES, LDS, LSS, LFS, LGS, CMPXCHG8B, CMPXCHG16B, F20FF0 "
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"LDDQU)."},
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{"N", "mm",
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"The R/M field of the ModR/M byte selects a packed quadword MMX "
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"technology register."},
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{"O", "moffs",
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"The instruction has no ModR/M byte; the offset of the operand is coded "
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"as a word, double word or quad word (depending on address size "
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"attribute) in the instruction. No base register, index register, or "
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"scaling factor can be applied (only MOV (A0, A1, A2, A3))."},
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{"P", "mm",
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"The reg field of the ModR/M byte selects a packed quadword MMX "
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"technology register."},
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{"Q", "mm/m64",
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"A ModR/M byte follows the opcode and specifies the operand. The "
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"operand is either an MMX technology register or a memory address. "
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"If it is a memory address, the address is computed from a segment "
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"register and any of the following values: a base register, an index "
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"register, a scaling factor, and a displacement."},
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{"R", "r",
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"The mod field of the ModR/M byte may refer only to a general "
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"register (only MOV (0F20-0F24, 0F26))."},
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{"S", "Sreg",
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"The reg field of the ModR/M byte selects a segment register (only MOV "
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"(8C, 8E))."},
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{"T", "TRn",
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"The reg field of the ModR/M byte selects a test register (only MOV "
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"(0F24, 0F26))."},
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{"U", "xmm",
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"The R/M field of the ModR/M byte selects a 128-bit XMM register."},
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{"sr", "32real",
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"Single-real. Only x87 FPU instructions (for example, FADD)."},
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{"dr", "64real",
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"Double-real. Only x87 FPU instructions (for example, FADD)."},
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{"er", "80real",
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"Extended-real. Only x87 FPU instructions (for example, FLD)."},
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{"e", "14/28", "x87 FPU environment (for example, FSTENV)."},
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{"V", "xmm",
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"The reg field of the ModR/M byte selects a 128-bit XMM register."},
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{"W", "xmm/m",
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"A ModR/M byte follows the opcode and specifies the operand. The operand "
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"is either a 128-bit XMM register or a memory address. If it is a memory "
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"address, the address is computed from a segment register and any of the "
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"following values: a base register, an index register, a scaling factor, "
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"and a displacement"},
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{"X", "m",
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"Memory addressed by the DS:eSI or by RSI (only MOVS, CMPS, OUTS, "
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"and LODS). In 64-bit mode, only 64-bit (RSI) and 32-bit (ESI) "
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"address sizes are supported. In non-64-bit modes, only 32-bit (ESI) "
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"and 16-bit (SI) address sizes are supported."},
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{"Y", "m",
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"Memory addressed by the ES:eDI or by RDI (only MOVS, CMPS, INS, "
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"STOS, and SCAS). In 64-bit mode, only 64-bit (RDI) and 32-bit (EDI) "
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"address sizes are supported. In non-64-bit modes, only 32-bit (EDI) "
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"and 16-bit (DI) address sizes are supported. The implicit ES "
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"segment register cannot be overridden by a segment prefix."},
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{"Z", "r",
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"The instruction has no ModR/M byte; the three least-significant "
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"bits of the opcode byte selects a general-purpose register."},
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{"F", "-", "rFLAGS register."},
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{"si", "32real",
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"Doubleword integer register (e. g., eax). (unused even by Intel?)"},
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{"ss", "-",
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"Scalar element of a 128-bit packed single-precision floating data."},
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{"stx", "512", "x87 FPU and SIMD state (FXSAVE and FXRSTOR)."},
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{"st", "94/108", "x87 FPU state (for example, FSAVE)."},
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{"s", "-",
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"6-byte pseudo-descriptor, or 10-byte pseudo-descriptor in 64-bit mode "
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"(for example, SGDT)."},
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{"bcd", "80dec",
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"Packed-BCD. Only x87 FPU instructions (for example, FBLD)."},
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{"bsq", "", "(Byte, sign-extended to 64 bits.)"},
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{"bss", "8",
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"Byte, sign-extended to the size of the stack pointer (for example, PUSH "
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"(6A))."},
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{"bs", "8", "Byte, sign-extended to the size of the destination operand."},
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{"a", "16/32&16/32",
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"Two one-word operands in memory or two double-word operands in memory, "
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"depending on operand-size attribute (only BOUND)."},
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{"b", "8", "Byte, regardless of operand-size attribute."},
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{"c", "?",
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"Byte or word, depending on operand-size attribute. (unused even by "
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"Intel?)"},
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{"dqp", "32/64",
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"Doubleword, or quadword, promoted by REX.W in 64-bit mode (for example, "
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"MOVSXD)."},
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{"dq", "128",
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"Double-quadword, regardless of operand-size attribute (for example, "
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"CMPXCHG16B)."},
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{"ds", "32",
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"Doubleword, sign-extended to 64 bits (for example, CALL (E8)."},
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{"di", "32int",
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"Doubleword-integer. Only x87 FPU instructions (for example, FIADD)."},
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{"d", "32", "Doubleword, regardless of operand-size attribute."},
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{"qi", "64int",
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"Qword-integer. Only x87 FPU instructions (for example, FILD)."},
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{"qp", "64", "Quadword, promoted by REX.W (for example, IRETQ)."},
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{"q", "64",
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"Quadword, regardless of operand-size attribute (for example, CALL (FF "
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"/2))."},
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{"v", "16/32",
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"Word or doubleword, depending on operand-size attribute (for example, "
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"INC (40), PUSH (50))."},
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{"wi", "16int",
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"Word-integer. Only x87 FPU instructions (for example, FIADD)."},
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{"w", "16",
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"Word, regardless of operand-size attribute (for example, ENTER)."},
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{"pi", "-", "Quadword MMX technology data."},
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{"psq", "-", "64-bit packed single-precision floating-point data."},
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{"pd", "-", "128-bit packed double-precision floating-point data."},
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{"ps", "-", "128-bit packed single-precision floating-point data."},
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{"ptp", "16:16/32/64",
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"32-bit or 48-bit pointer, depending on operand-size attribute, or 80-bit "
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"far pointer, promoted by REX.W in 64-bit mode (for example, "
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"CALLF (FF /3))."},
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{"p", "16:16/32",
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"32-bit or 48-bit pointer, depending on operand-size attribute (for "
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"example, CALLF (9A)."},
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};
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void HandleOperand(const char *op) {
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int i;
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bool found;
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while (*op) {
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found = false;
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for (i = 0; i < ARRAYLEN(kDescriptors); ++i) {
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if (startswith(op, kDescriptors[i].prefix)) {
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found = true;
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op += strlen(kDescriptors[i].prefix);
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if (succinct_) {
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printf("%s ", kDescriptors[i].succinct);
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} else if (!isempty(kDescriptors[i].succinct) &&
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strcmp(kDescriptors[i].succinct, "-") != 0 &&
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strcmp(kDescriptors[i].succinct, "?") != 0) {
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printf("%s (%s): %s\n", kDescriptors[i].prefix,
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kDescriptors[i].succinct, kDescriptors[i].description);
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} else {
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printf("%s: %s\n", kDescriptors[i].prefix,
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kDescriptors[i].description);
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}
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break;
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}
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}
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if (!found) {
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printf("%c?", *op);
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if (succinct_) {
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printf(" ");
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} else {
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printf("\n");
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}
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op++;
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}
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}
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printf("\n");
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}
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int main(int argc, char *argv[]) {
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int i;
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GetOpts(argc, argv);
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for (i = optind; i < argc; ++i) {
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HandleOperand(argv[i]);
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}
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return 0;
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}
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